The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2003
Filed:
May. 25, 2002
Pablo D'Anna, Redding, CA (US);
Joseph H. Johnson, Phoenix, AZ (US);
Sirenza Microdevices, Inc., Sunnyvale, CA (US);
Abstract
A microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type overlaying the top surface of the semiconductor substrate and having a top surface; (c) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (d) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (e) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (f) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region; (g) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (h) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; wherein the shield plate region is adjacent and parallel to the conductive gate region; and wherein the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top-surface of the silicon semiconductor material; and (i) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.