The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2003

Filed:

May. 11, 1999
Applicant:
Inventors:

Jeff Erhardt, San Jose, CA (US);

Bin Yu, Sunnyvale, CA (US);

G. Jonathan Kluth, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.


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Erhardt, Jeff. (2003). Method of forming a cmos transistor having ultra shallow source and drain regions (U.S. Patent No. 6521501). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6521501

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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