The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2003

Filed:

Sep. 29, 1999
Applicant:
Inventors:

Frederick H. Fischer, Macungie, PA (US);

Srinivasa Gutta, Allentown, PA (US);

Vladimir Sindalovsky, Perkasie, PA (US);

Assignee:

Agere Systems, Inc., Berkeley Heights, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 ; G06F 1/09 ; H03K 1/9003 ;
U.S. Cl.
CPC ...
G06F 1/04 ; G06F 1/09 ; H03K 1/9003 ;
Abstract

A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.


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