The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2003
Filed:
Apr. 06, 2000
Wayne C Bowman, Allen, TX (US);
Chris Morrow Young, Rockwall, TX (US);
Other;
Abstract
A method for determining the effect of load impedance on the magnitude and phase of loop gain of a power converter apparatus to aid in predicting stability of the converter apparatus under various operating conditions. The converter apparatus has an open-loop output impedance and provides an output signal to an output locus. The method comprises the steps of: (a) vectorally measuring a first loop gain of the converter apparatus with a first load impedance connected with the output locus, to record phase and gain of the first loop gain for a plurality of frequencies; (b) vectorally measuring open loop output impedance as a function of frequency of the converter apparatus, to record phase and gain of the open loop output impedance for a plurality of frequencies; (c) vectorally measuring the first load impedance as a function of frequency of the converter apparatus, to record phase and gain of the first load impedance for a plurality of frequencies; (d) calculating a first load distribution factor using the first load impedance and the open-loop output impedance; the calculating being effected in vectoral manner to record magnitude and phase of the first load distribution factor for a plurality of frequencies; (e) selecting a second impedance load with an output voltage sense point, the second impedance load being representable by a network of at least one resistor and at least one capacitor or inductor, the output voltage sense point being situated at a selected node of the network; (f) calculating a second load distribution factor for the second impedance load using the open-loop output impedance and the second impedance load; the calculating being effected in vectoral manner to record magnitude and phase of the impedance-loop load distribution factor for a plurality of frequency values; and (g) calculating a second loop gain using the first loop gain, the first loop load distribution factor and the second loop load distribution factor; the calculating being effected in vectoral manner to record magnitude and phase of the impedance-load gain for a plurality of frequency values.