The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2003
Filed:
Oct. 14, 1999
Michael John Brady, Brewster, NY (US);
Venkata S. R. Kodukula, Yorktown Heights, NY (US);
Intermec IP Corp., Woodland Hills, CA (US);
Abstract
The present invention is directed to an ultra-thin outline package for integrated circuits that is much smaller than conventional chip packaging structures. The ultra-thin outline package is particularly useful in fabricating RF or RFID transponders. In an embodiment of the invention, the ultra-thin outline package includes a substrate having an aperture. At least one conductive trace that includes upper and lower portions is disposed on respective upper and lower surfaces of the substrate. The substrate further comprises at least one via electrically connecting the conductive trace portions together. An integrated circuit is disposed in the aperture and is operatively coupled to the upper portion of the conductive trace. An encapsulant is provided in the aperture substantially covering the integrated circuit. The lower portion of the conductive trace is adapted for coupling of the ultra-thin outline package to a secondary substrate using conventional surface mounting techniques. The via connecting the upper and lower trace portions may be disposed either on at least one edge surface of the aperture or on at least one edge surface of the substrate. At least one wire bond electrically couples the integrated circuit to the conductive trace, and the encapsulant covers the integrated circuit and the wire bond. Using printed circuit board material for the substrate, the ultra-thin outline package achieves a vertical profile of approximately 0.3 to 0.375 mm (12 to 15 mils).