Clock generating circuit and semiconductor integrated circuit using the same

Abstract

A clock generating circuit for generating a clock signal of which frequency is variable, has a delay circuit a selector and a control circuit The delay circuit has buffers to for delaying the input clock signal and output terminals A to D each of which outputs a clock signal delayed by a different delay time. The selector selects one of the output terminals in the delay circuit based on the output from the control circuit The control circuit supplies an output signal formed of a group of bits that is circulated in a predetermined cycle, to the selector A cycle in an output clock signals OUT sequentially outputted from the output terminal through the output terminals selected by the selector increases or decreases in accordance with the group of bits in the output signal. Thus, the frequency in the output clock signal OUT will vary to reduce EMI noise.