Alias suppression method for 1-bit precision direct digital synthesizer

Abstract

The present invention provides an improved apparatus and technique for removing alias signals from the output of a discretely timed circuit. Rather than simply lowpass filtering an output signal from a discretely timed circuit signal to remove aliases as in conventional discretely timed circuits, and instead of increasing the frequency of the clock signal in other conventional discretely timed circuits, the present invention provides for interpolation between clock edges, taking advantage of information in the digital representation, to reduce or eliminate many lower-order alias signal components. More particularly, the present invention eliminates lower-order aliases of a discretely timed circuit, e.g., of a 1-bit resolution direct digital synthesizer (DDS) by interpolating transitions within clock periods utilizing the period of the signal and its instantaneous phase, to improve the time resolution of the output signal. In a disclosed embodiment, a multiplier produces product of an output signal (e.g., from a phase accumulator) and its period (e.g., output from a period register). The disclosed interpolator includes a digital comparator and a varying reference generator, e.g., a ramp generator, together with an appropriate digital-to-analog converter, to set a threshold proportional to the phase-period product. If the product of the multiplier is greater than unity, a transition is prohibited. However, if the product of the multiplier is less than or equal to unity, a transition occurs, preferably within the next clock period.