The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Oct. 10, 2000
Masahiro Fukui, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A layout structure and a method for generating a layout for an integrated circuit more efficiently to catch up with remarkable developments of fabrication technologies of today. In generating a layout for a CMOS circuit, a pair of p- and n-channel transistors is used as a layout unit if one of these transistors is the dual of the other. These two transistors of are placed closely to each other so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, those wires can be extended substantially vertically to each other.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile