The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Feb. 09, 2001
Yung-Chi Hwang, Sanchung, TW;
Acer Laboratories Inc., Taipei Hsien, TW;
Abstract
A data processing system and a method for accessing data therein. The data processing system includes a microprocessor, an application specific integrated circuit (ASIC), and a memory. The ASIC is coupled between the microprocessor and the memory and is utilized to communicate with an external computer system for downloading a program code from the external computer system to the memory in which the program code is stored in a memory region of the memory through the ASIC. In addition, the ASIC is for mapping the memory region onto an external memory address space of the microprocessor. The microprocessor generates an address latch enable (ALEN) signal, program memory enable (PMEN) signal, read enable (RDEN) signal, write enable (WREN) signal, and a first address signal. The ASIC, during the enabling period of the ALEN signal, receives the first address signal, converts the first address signal into a second address signal corresponding to an address in the memory region, and reads a first data from the memory according to the second address signal. When the PMEN or RDEN signal is enabled, the ASIC converts the first data into a second data and sends the second data to the microprocessor. When the WREN signal is enabled, the microprocessor sends a third data to the ASIC and the ASIC converts the third data into a fourth data and writes the fourth data into the memory according to the second address signal.