The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Oct. 26, 2000
Kendell A. Chilton, Southborough, MA (US);
Daniel Castel, Framingham, MA (US);
EMC Corporation, Hopkinton, MA (US);
Abstract
The invention is directed to techniques for accessing data within a data storage system having a circuit board that includes both a front-end circuit for interfacing with a host and a back-end circuit for interfacing with a storage device. To move data between the host and the storage device, an exchange of data between the front-end circuit and the back-end circuit can occur within the circuit board thus circumventing the cache of the data storage system. Such operation not only reduces traffic through the cache, but also shortens the data transfer latency. In one arrangement, a data storage system includes a cache, a first front-end circuit that operates as an interface between the cache and a first host, a second front-end circuit that operates as an interface between the cache and a second host, a first storage device (e.g., a disk drive, tape drive, CDROM drive, etc.), a second storage device, a first back-end circuit that operates as an interface between the cache and the first storage device, and a second back-end circuit that operates as an interface between the cache and the second storage device. The first front-end circuit and the first back-end circuit reside on a first circuit board. Similarly, the second front-end circuit and the second back-end circuit reside on a second circuit board. Accordingly, data transfer between the first host and the first storage device can occur through the first front-end circuit and the first back-end circuit (both of which are on the first circuit board) and circumvent the cache. Likewise, data transfer between the second host and the second storage device can occur through the second front-end circuit and the second back-end circuit (both of which are on the second circuit board) and circumvent the cache. Such data transfers decreases traffic through the cache and reduces data retrieval latencies for non-cached read operations.