Dequeuing logic architecture and operation in a multiport communication switch

Abstract

A multiport data communication system for switching data packets between ports having a memory storing received data packets and a plurality of ports for transmitting and receiving data packets. Each transmit port has a transmit queue storing data packets to be transmitted from the respective port. The system includes a plurality of output queues, each corresponding to a respective port and storing frame pointers that point to where the data packets are stored in the memory. A plurality of dequeuing logic circuitry is provided corresponding to the plurality of ports. Each dequeuing logic circuitry reads respective frame pointers from the plurality of queues, reads the respective data packets corresponding to the respective frame pointers from the memory, and writes each read data packet to the corresponding transmit queue. The operations of each dequeuing logic circuitry are carried out in a pipelined manner in order to fully utilize the bandwidth of the external memory and speed up the dequeuing process. Consequently, there is no idle time between completing of reading of one data packet from the memory and beginning of reading of a subsequent data packet from the memory or between completing writing of one data packet to the corresponding transmit queue and 4.