The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Dec. 18, 2001
Stefan P. Sywyk, San Jose, CA (US);
Eric H. Voelkel, Ben Lomond, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
According to one embodiment, a content addressable memory (CAM) can include at least one match line ( ), series-coupled transistor pairs comprising match transistors ( - to -n) and switch devices ( - to -n), bit match indicator signals ( - to -n), mask cell value signals ( - to -n), a match line precharge limiting device ( ), a match line precharge control device ( ) and an amplifier circuit ( ). This configuration can allow for the regulation of the match line ( ) discharge path through a discharge control device ( ) and a match indication feedback device ( ). This, in turn, can allow for match line ( ) precharging while at least one of the bit match indicator signals ( - to -n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands. As such, the pseudo-VSS ( ) line control may prevent a static current path from developing during the precharge scenario described above by directly controlling the path between the pseudo-VSS ( ) line and the circuit ground supply.