The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2003

Filed:

Jun. 29, 2000
Applicant:
Inventor:

Yuso Udo, Chofu, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03B 2/742 ; G03B 2/752 ; G03B 2/732 ;
U.S. Cl.
CPC ...
G03B 2/742 ; G03B 2/752 ; G03B 2/732 ;
Abstract

A semiconductor wafer having an effective chip region set within an effective element region in which an element is formed and required for forming a single chip and an ineffective chip region which includes an ineffective element region in which no element is formed and required for forming a single chip. A degree of unevenness of a surface of the semiconductor wafer is measured at a plurality of sites within a predetermined region by an unevenness measuring section by applying light thereof, so that unevenness data are output. The predetermined region includes either or a part of both of the effective chip region and the ineffective chip region. A reference plane to which light is applied is determined by using only unevenness data of the effective chip region after unevenness data of the ineffective chip region are eliminated from the unevenness data. Inclination of the semiconductor wafer is controlled in accordance with the reference plane obtained through the calculation performed by the calculating section.


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