The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Sep. 26, 2001
Applicant:
Inventors:
Yohei Ishikawa, Kyoto, JP;
Kenichi Iio, Nagaokakyo, JP;
Takatoshi Kato, Mino, JP;
Koichi Sakamoto, Otsu, JP;
Assignee:
Murata Manufacturing Co. Ltd, , JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01P 3/08 ;
U.S. Cl.
CPC ...
H01P 3/08 ;
Abstract
Electrodes are formed on both top and bottom surfaces of a dielectric plate and grounded coplanar lines, as transmission lines, are formed on the top surface of the dielectric plate. A plurality of micro-strip lines, each composed of high-impedance lines and low-impedance lines alternately connected in series, is arranged at a pitch shorter than the wavelength of a wave traveling along the grounded coplanar lines. A spurious mode propagation blocking circuit thus constructed prevents a spurious mode wave, such as a parallel-plate mode, from traveling.