The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
May. 30, 2000
Masayuki Miyazaki, Tokyo, JP;
Ken Tatezawa, Kodaira, JP;
Kiwamu Takada, Kodaira, JP;
Kunio Uchiyama, Kodaira, JP;
Osamu Nishii, Inagi, JP;
Kiyoshi Hasegawa, Fusa, JP;
Hirokazu Aoki, Hachioji, JP;
Masaru Kokubo, Hanno, JP;
Other;
Abstract
A signal from a crystal resonator or an external clock signal are input from terminals xta or exta and the signal from the crystal resonator or external clock signal are selected by mode terminal mod and input to an oscillator OSC. An input clock signal ckl is frequency-divided to desired values by a divider DIV A divided clock signal clk is input as the reference clock of a phase-locked loop PLL or delay-locked loop DLL and a clock signal output by a circuit selected by a selector SEL passes via a divider DIV to be distributed to an LSI. The phase-locked loop PLL has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL is 2-3 periods.