The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Feb. 26, 1999
Kyu Hyun Choi, Cupertino, CA (US);
Ace Memory, Inc., Cupertino, CA (US);
Abstract
A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000A and small spaces down to 700 Å. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 Å comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material. Portions of the product material which are not protected by the masking material are removed to leave a desired width of product material corresponding to the width of the masking material. The corresponding process can be used to form spacings of corresponding dimensions.