Fifo system with variable-width interface to host processor

Abstract

A computer system includes a RAM-based FIFO for buffering communications between a host processor and a remote serial-communications device. The FIFO provides for quadlet, doublet, and singlet transfer widths depending on the memory-mapped IO address asserted by the processor. Quadlet transfers can be implemented until the amount of data remaining to be transferred is less than four bytes. For each quadlet transfer, the read pointer, in the case of a read operation, or the write pointer, in the case of a write operation, is incremented by four. If two or three bytes of data remain after the quadlet transfers, a doublet transfer can be implemented; in this case, the appropriate pointer is incremented by two. Finally, if a byte of data remains after the quadlet transfers and a possible doublet transfer, then a singlet transfer is effected. In this case, the appropriate pointer is incremented by one. For example, 31 bytes of data in an 8×4-byte FIFO can be transferred in seven quadlet transfers, one doublet transfer, and one byte-wide transfer. The use of the wide transfers greatly reduces the processor overhead in servicing the FIFO, making more processor power available to concurrently running tasks and improving system performance overall.