The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2003

Filed:

Jan. 10, 2000
Applicant:
Inventor:

Yoshiaki Nakano, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/01 ; H01P 1/213 ;
U.S. Cl.
CPC ...
H03H 7/01 ; H01P 1/213 ;
Abstract

A spurious signal reduction circuit which is connected to a main signal line. The spurious signal reduction circuit comprises a resistor having a terminal connected to the main signal line, an LC parallel resonance circuit and an LC series resonance circuit. The parallel resonance circuit has a resonance frequency which is equal to a main signal frequency and has a terminal connected to another terminal of the resistor. The series resonance circuit has a resonance frequency which is equal to a spurious signal frequency and has a terminal connected to the other terminal of the resistor.


Find Patent Forward Citations

Nakano, Yoshiaki. (2003). Spurious signal reduction circuit (U.S. Patent No. 6512427). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6512427

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…