The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2003
Filed:
Jun. 28, 2001
James C. Dunphy, San Jose, CA (US);
William J. Cummings, San Francisco, CA (US);
Colin D. Stanners, San Jose, CA (US);
Lawrence S. Pan, Los Gatos, CA (US);
Candescent Technologies Corporation, San Jose, CA (US);
Abstract
Methods for performing cathode burn-in with respect to an FED display that avoid display non-uniformities near and around the spacer wall structures. In a first method, the anode is floated or receives a negative voltage with respect to the electron emitter. A positive voltage is then applied to the focus waffle structure with respect to the electron emitter. The cathode is then energized thereby preventing emitted electrons from escaping the focus well. Under these conditions, cathode burn-in conditioning can occur but electrons are energetically forbidden from hitting the anode or the spacer walls except for a small region near the focus waffle. Under the second method, the anode is grounded or allowed to float. A negative bias is applied to the focus waffle. This causes electrons to be collected at the M layer of the gate. Electrons are energetically forbidden from hitting any portion of the tube except the M layer. Under either method, no electrons hit the spacer walls and therefore display non-uniformities near and around the spacer wall structures are avoided.