Reverse mask and nitride layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems

Abstract

Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in poor RC time constants of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated or substantially reduced by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second and third dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer, thereby serving as a partial etch stop layer preventing deleterious over-etching of the borderless via.