The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2003

Filed:

Mar. 03, 2000
Applicant:
Inventors:

David Matt, Missouri City, TX (US);

Marulkar Rajendra Sadanand, Pune, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C06F 1/200 ;
U.S. Cl.
CPC ...
C06F 1/200 ;
Abstract

A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address (often representing a “page”) are compared against one or more reference registers to yield one or more “match_high”s. The lower bits of the same bus address are used to look-up the value of “match_low” in a Page Look-Up RAM the bit of interest corresponding to the particular “match-high” reference register i.e. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.


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