The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2003

Filed:

Feb. 27, 2001
Applicant:
Inventors:

Naritoshi Saito, Hino, JP;

Yutaka Asanuma, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 2/706 ;
U.S. Cl.
CPC ...
H04L 2/706 ;
Abstract

A multiplier multiplies a baseband signal with a scramble code generated by a CPICH scramble code generator and an integrator integrates the result of the multiplication. A symbol selection control unit controls the integrator such that the integrator integrates each of two successive slots in which combinations of the symbols transmitted from two antennas of a base station are the same, in accordance with the information about the synchronous positions of the slots and frames. The result of the integration is delayed by a 1-symbol delay unit and then a code of a complex component is inverted by a complex conjugate unit. A multiplier multiplies the outputs of the integrator and complex conjugate unit, which are shaped in a complex number, to obtain an amount of phase rotation between the successive symbols, i.e. a frequency error.


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