Adjustable clock multiplier and method

Abstract

An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier. When the pulse count is too low, the limiter outputs an ADJUST UP signal which speeds up the output cycle time of the clock multiplier. The ADJUST DOWN/UP signals are preferably provided to a register which maintains and outputs a string of control signals for controlling a set of delay elements within a programmable delay circuit. The programmable delay circuit optionally includes a tap point multiplexer for varying the number of delay elements in the delay path, to provide greater range of frequency multiple and faster lock.