Method and circuit arrangement for using two processors to read values of two independently clocked counters, exchanging values therebetween, comparing two values to determine error when the comparison exceed a threshold

Abstract

A system is described for reliable monitoring of clock rates, where a first processor which receives a first clock rate causes a counter to count using this first clock rate. A second processor which receives a second clock rate also causes another counter to count using the second clock rate. The readings of the counters are stored by the processors at predefined intervals in a common memory. Subsequently each of the processors loads the counter reading of the other processor, and compares it with its own counter reading. If both readings are within a tolerance range, one of the counter readings is used as a reference for all the other counters and the other counter readings are made equal to this reference value, so that subsequent monitoring of the processors is based on this reference value for the respective counters. If a reading is outside the tolerance range, an error is triggered.