The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2003
Filed:
Aug. 13, 1999
John G McBride, Ft Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network. In accordance with the preferred embodiment of the present invention, the rules checker algorithm performs these tasks by: (1) analyzing each branch of the network to determine the primary RC delay of each branch assuming the branch being analyzed corresponds to the worst case RC delay of the network; (2) analyzing each branch of the network assuming one of the other branches of the network corresponds to the worst case RC delay of the network and determining the effect that the resistances and capacitances of the branch being analyzed would have on other branches; (3) determining the total effective RC delay of each branch by combining the primary RC delay of each branch with the effect that the other branches have on the branch being analyzed; and (4) determining which branch of the network has the largest total effective RC delay.