The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2003
Filed:
Sep. 22, 2000
Takuma Aoyama, Dusseldorf, DE;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A voltage controlled delay circuit comprising n-type inverter delay circuits comprised of n-type inverters each having a PMOS transistor, as a load, with a source connected to a power supply node and with a gate to which a delay time amount control voltage is applied and having an NMOS transistor for driving, an NMOS transistor for bias with a drain-source pass connected between a ground node and a node at which sources of NMOS transistors of the inverter delay circuits each as a stage are commonly connected and with a gate to which a bias voltage to set to be “ON” is applied, and a push-pull inverter circuit which inputs a signal of which the amplitude changes over the entire amplitude in a range of power supply voltage to a first-stage delay circuit.