The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2003

Filed:

May. 17, 2001
Applicant:
Inventor:

Andrej Litwin, Danderyd, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 3/10312 ;
U.S. Cl.
CPC ...
H01L 3/10312 ;
Abstract

A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m. The distances from the long sides of the rectangular area to the edges of the chip should be at least 50% and preferably 60% of the thickness of the chip to allow a good thermal flow out of the active rectangular area. A plurality of such very elongated active areas can be located on a single chip.


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