The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2003

Filed:

Mar. 25, 1999
Applicant:
Inventors:

Miguel Santana, Jr., Austin, TX (US);

Markangelo S. D'Souza, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/358 ;
U.S. Cl.
CPC ...
H01L 2/358 ;
Abstract

A method for position-selective and material-selective etching of silicon, and examination structures formed using the method, are presented. A semiconductor topography is exposed to an electron beam in the presence of xenon difluoride (XeF ) gas. The beam is scanned over a portion of the semiconductor topography, and silicon portions of the topography contacted by the electron beam and the XeF gas are etched. Non-silicon portions, such as dielectrics, metals, and/or metal silicides, are not believed to be etched. Shorter exposure times may be used to remove polycrystalline silicon portions of a topography, while leaving monocrystalline silicon portions intact. Removal of silicon and non-silicon portions of the topography by other means may be used to expose silicon portions of the topography. The electron beam controlled etching recited herein may be used alone or combined with such removal by other means to form examination structures for use in evaluation of semiconductor manufacturing techniques.


Find Patent Forward Citations

Santana, Jr., Miguel. (2003). Position-selective and material-selective silicon etching to form measurement structures for semiconductor fabrication (U.S. Patent No. 6507044). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6507044

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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