Automatic cell placement and routing method and semiconductor integrated circuit

Abstract

A logical net list of cells and nets through which the cells are connected with each other is prepared. The cells are composed of a timing-free cell, in which an input timing of a signal is not considered, and a plurality of timing-considered cells in which an input timing of a signal is considered. Also, dummy pin information is prepared to specify the timing-free cell because the design of a layout pattern of the timing-free cell is not desired. The correspondence of the dummy pin information to the logical net list is established to isolate the timing-free cell from the timing-considered cells by placing dummy pins on both sides of the timing-free cell. Thereafter, the correspondence of timing information to the logical net list is established to allocate timing information to each timing-considered cell, positions of the dummy pins in a layout pattern of the timing-considered cells to be designed are indicated by dummy pin layout-position information, and an automatic layout routing based on a timing driven layout technique is performed for the timing-considered cells. Accordingly, even though the timing-free cell is placed on a signal path with the timing-considered cells, a layout pattern of the timing-considered cells can be designed, a design time can be shortened, and a design efficiency can be improved.