The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2003
Filed:
Aug. 28, 2000
Applicant:
Inventor:
Genichi Tanaka, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
There is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step which comprises the steps of, based on design information completed to a placement step, determining a wiring route considering a shape of a via and/or the number of the via, estimating the number of routing tracks to be used in each search of the global routing step, and verifying the estimated result, thereby obtaining a layout according to a wiring estimate at the global routing step.
Tanaka, Genichi. (2003). Automatic placement and routing of semiconductor integrated circuits (U.S. Patent No. 6505333). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6505333
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile