Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuit memory devices using bit cell detection and depth first searching techniques

Abstract

A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell. This tracing operation preferably comprises tracing a netlist path extending from the first device to a first bit line or a first word line electrically connected to the first memory cell. This netlist path may include a path defined by one or more nets and devices connected together and preferably connected between the first device and the first bit line (or first word line). The first bit line and/or first word line is then traced locally to identify a plurality of additional memory cells electrically coupled thereto along a column or row. Additional bit lines and words lines that are connected to these identified memory cells can also be traced in a similar manner to identify a plurality of rows and columns of memory cells in a memory array block.