The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2003

Filed:

Feb. 15, 2001
Applicant:
Inventors:

Kenneth T. Chin, Cypress, TX (US);

C. Kevin Coffee, Pembroke Pines, FL (US);

Michael J. Collins, Pleasonton, CA (US);

Jerome J. Johnson, Spring, TX (US);

Phillip M. Jones, Spring, TX (US);

Robert A. Lester, Houston, TX (US);

Gary J. Piccirillo, Cypress, TX (US);

Jeffrey C. Stevens, Spring, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/318 ;
U.S. Cl.
CPC ...
G06F 1/318 ;
Abstract

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.


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