The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2003
Filed:
Apr. 10, 2002
Nobuyuki Kokubo, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A load circuit for coupling a bit line pair BLP in a memory cell array to a power supply potential makes a bit line once to a floating state when the mode shifts to a standby mode in accordance with a chip select signal /CS. The load circuit holds the potential of the bit line BL in a latch circuit and determines whether the bit line BL is coupled to the power supply potential or not in accordance with the held potential. Therefore, in the case where a small short circuit occurs between the bit line and the ground line, the bit line is disconnected from the power supply potential, thereby enabling the current in the standby mode to be reduced.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile