The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6502224 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 31, 2002

Filed:

Apr. 12, 2001
Applicant:
Inventors:

Sang Hoo Dhong, Austin, TX (US);

Harm Peter Hofstee, Austin, TX (US);

Stephen Douglas Posluszny, Round Rock, TX (US);

Joel Abraham Silberman, Somers, NY (US);

Osamu Takahashi, Round Rock, TX (US);

Dieter F. Wendel, Schoenaich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.


Find Patent Forward Citations

Dhong, Sang. (2002). Method and apparatus for synthesizing levelized logic (U.S. Patent No. 6502224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6502224

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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