The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2002

Filed:

Oct. 10, 2001
Applicant:
Inventor:

Yasuhiko Maki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

Precharge circuits comprises PMOS transistors Q and Q each connected between a bit line and a power source potential VDD, PMOS transistors Q Q Q and Q connected between respective bit line pairs, and PMOS transistors Q and Q connected between respective adjacent bit lines of adjacent bit line pairs, wherein the gate electrodes of the PMOS transistors are each connected to a precharge control signal line PCG. The defect caused by omission of transistors from the prior art circuits is compensated by the PMOS transistors Q and Q each of which is required to be provided for two bit line pairs. With this and transistors of adjacent unit precharge circuits are arranged in plain symmetry, there is no need to provide transistors to be directly connected between bit lines *B and B and an average number of PMOS transistors for each bit line pair is less than 2.5.


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