High speed, low-power cmos circuit with constant output swing and variable time delay for a voltage controlled oscillator

Abstract

A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors and with an NMOS transistor providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors and provide loads for the differential transistor and . Transistors and together with an amplifier provide biasing for the delay device. The amplifier has a non-inverting input set to V −V . As configured, a constant output voltage swing from V to V −V is provided at the outputs V + and V − of the delay device, independent of a control voltage V used to set the tail current. The NMOS load transistor , as opposed to the PMOS transistor in FIG. , does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current. A wide frequency tuning range of a ring oscillator using the delay circuit of FIG. is provided because the operating frequency for a ring oscillator will be directly proportional to the tail current through transistor