The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6501126 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 31, 2002

Filed:

Feb. 15, 2001
Applicant:
Inventor:

Arto Rantala, Espoo, FI;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/776 ;
U.S. Cl.
CPC ...
H01L 2/776 ;
Abstract

The invention relates to a semiconductor structure and a method for minimizing non-idealities in a semiconductor structure, in which a drain; a source, a floating gate ( ) and at least one input ( ) capacitively connected'to the floating gate ( ) are disposed on a substrate ( ) so as to form a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate ( ) and at least partially superimposed on the gate ( ) is formed in the semiconductor structure and the conductive layer is connected to a constant potential.


Find Patent Forward Citations

Rantala, Arto. (2002). Semiconductor structure and procedure for minimizing non-idealities (U.S. Patent No. 6501126). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6501126

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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