The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2002

Filed:

Jan. 07, 2000
Applicant:
Inventor:

Brian T. Deng, Richardson, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/336 ; G06F 1/314 ; G06F 1/300 ; G06F 1/12 ; G06F 1/04 ;
U.S. Cl.
CPC ...
G06F 1/336 ; G06F 1/314 ; G06F 1/300 ; G06F 1/12 ; G06F 1/04 ;
Abstract

A post write buffer for a dual clock system which improves the utilization of host data bus ( ) bandwidth is provided which consists of an address buffer ( ), a data buffer ( ), a first clock timing signal ( ), a second clock timing signal ( ), an address decoder ( ), a first write enable circuit ( ), and a second write enable circuit ( ). The address-buffer ( ) and data buffer ( ). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder ( ) determines which destination register byte will receive the data in the host data bus ( ). The write enable circuits ( ) synchronize the clock signals ( ) and determine when the destination register is ready to receive the data from the data buffer ( ).


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