The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2002
Filed:
Jul. 24, 2000
Brian G. Reise, Colorado Springs, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A simulation test bench environment for testing a circuit is described. The test bench environment uses high-level task routines executed by one or more bus functional device models to generate input test vectors. A timing and protocol checker verifies both signal timing and functional operation bus specifications. Data and parity miscompares and corruptions are reported in real-time during simulation. An error and interrupt handler services errors and interrupts by communicating with the buses coupled to the circuit to execute specific recovery routines. A memory model is used to generate known expected data for data transactions, to store data from the circuit on data transactions, and to generate operation codes for the circuit.