The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2002
Filed:
Feb. 15, 2001
Mark Peting, Tigard, OR (US);
Thad McCracken, Portland, OR (US);
Digeo, Inc., Kirkland, WA (US);
Abstract
The invention provides an efficient structure for synthesized static arrays. Array structures are very common in chip design, and often when doing ASIC design the option of custom-designing these arrays does not exist, therefore necessitating that the arrays be synthesized, placed and routed on silicon in a manner similar to random logic. Standard array structures are not easily synthesized, placed and routed. The invention takes advantage of the case in which the design requirements are such that the array is loaded in whole and then remains static for a period of time. The array implementation writes one column of the array (instead of a row) at a time so that the desired contents of the array are “rotated” 90 degrees before being written to the array. This allows the latches in a column to share a gated clock signal, which allows for an array placement optimized for clock distribution and for general routing density.