The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6498504 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 24, 2002

Filed:

Aug. 27, 2001
Applicant:
Inventor:

Yuji Miyagi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/102 ;
U.S. Cl.
CPC ...
G01R 3/102 ;
Abstract

The wafer inspection device carries out inspection of a plurality of integrated circuits provided with a plurality of electrode pads, respectively, in a condition where the integrated circuits are formed on a wafer. The wafer inspection device is provided with a test head for outputting a test pattern from a plurality of tester pogo pins, a test board to which the tester pogo pins are connected, and a substrate. A plurality of contact pins that correspond to the tester pogo pins, respectively, and are arranged in a matrix form are provided on the test board. A plurality of first terminals, which are connected, respectively, to the plurality of electrode pads, are provided on a first main surface of the substrate. A plurality of second terminals, which comprise terminal groups for each integrated circuit, are provided on a second main surface of the substrate. The terminal groups are arranged in a matrix form, and the second terminals are connected to the contact pins for each terminal group. Furthermore, inner wiring that connects the first and second terminals is provided in the substrate.


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