Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper

Abstract

A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.