The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Aug. 18, 1999
Hitachi, Ltd., Tokyo, JP;
Abstract
In a computer-aided design (CAD) method for the intra-chip wiring in a hierarchical implementation design of a semiconductor integrated circuit, wiring pattern spaces from block edge terminals are guaranteed while preventing any wiring detour in inter-block nets. Logical line connecting information and implementation information such as contours of parts and terminal positions are inputted from a logical file and a library to extract block edge terminals so as to define a block boundary in accordance with layout positions of parts to be allocated. On the block boundary defined, one virtual terminal is generated for each block edge terminal to dispose wirings between the block edge terminals and the associated virtual terminals. An intra-block net wiring is then achieved without a short circuit to the wirings between the block edge terminals and the associated virtual terminals. Finally, the virtual terminals and the wiring pattern between the block edge terminals and the associated virtual terminals are deleted.