The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Mar. 23, 2001
Masuo Inui, Kasugai, JP;
Takashi Yoneda, Kasugai, JP;
Rieko Toki, Kasugai, JP;
Hiroyuki Yamamoto, Kawasaki, JP;
Kenji Suzuki, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. First, a power supply type name is given to each power supply in accordance with the purpose of the power supply in each logic element. Each logic element is associated with the power supply type name of the power supply that is to be provided to the logic element. A power supply group is formed for each power supply. Specific information of each power supply group associating the power supply type name with supplied voltage is generated. Then, the power supply provided to each logic element is determined by allocating the power supply group to the logic element. The method simplifies designing the layout of a semiconductor device operated by multiple power supplies.