The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Apr. 04, 2001
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
In design of particularly large-scale, complicated semi-conductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.