Shared i/o ports for multi-core designs

Abstract

The present invention provides a shared I/O port and a configurable interconnect allowing any of a plurality of cores to access any pin of a shared I/O port. Preferably, one of the plurality of cores is designated as a master core at least with respect to the configuration of the shared I/O port(s), and the remaining cores desiring to gain access to the shared I/O port(s) are designated as non-master or slave cores. It is the responsibility of the master core to reassign chip resources such as the shared I/O port(s) for use by either the master core or by any of the shared cores. Preferably, all shared I/O ports are controlled by default by the master core. The slave cores communicate with the master core through a suitable internal messaging system. If a slave core requires use of a particular I/O pin or I/O port not already configured appropriately for its use, the slave core will send an appropriate message to the master core through the messaging system, e.g., a dual port memory mailbox. Preferably, the master core will then pass a message back to the requesting slave core indicating completion of the requested reconfiguration. The master core preferably keeps track of which core currently has control of each I/O pin or port using appropriate internal registers. The master core communicates with the relevant I/O pin or port using its I/O data bus, while the slave core communicates with the relevant I/O pin or port using its I/O data bus. IOP configuration signals from the master core configure and thus determine which core in the multi-core integrated circuit or hybrid circuit has access to I/O control modules or registers to control the direction, mode, interrupt generation capability, and/or status of the shared I/O port(s).