Time interleaved digital signal processing in a read channel with reduced noise configuration

Abstract

A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof. The conversion channel further includes an offset circuit for compensating an offset in the pair of analog-to-digital converters in the time interleaved analog-to-digital converter. The offset circuit is controlled by the digital post-processing circuit, and includes first and second distinct offset compensating circuits independently controlled by the digital post-processing circuit.