Modular architecture for image transposition memory using synchronous dram

Abstract

A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory banks are interleaved on the store operation such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency of the memory. Accordingly, consecutive groups of samples may be stored into the alternating memory banks continuously. When image data are read from memory, the memory read operations are not interleaved. To compensate for the set-up latency in the read operations, the controller advances the first read operation for a particular image line or image column into the horizontal or vertical blanking interval by an amount of time equal to the total latency for the line or column. The system includes a first in first out (FIFO) buffer which receives the image data as it is provided from the memory in response to the memory read requests and provides the image data according to the output timing for the transpose memory.