The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
May. 09, 2001
Applicant:
Inventors:
Stephen Myles Prather, Austin, TX (US);
Jeffrey William Waldrip, Austin, TX (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 ;
U.S. Cl.
CPC ...
H03K 3/01 ;
Abstract
A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.