The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2002

Filed:

Dec. 13, 2001
Applicant:
Inventors:

Robert W. Moss, Longmont, CO (US);

Peter Korger, Frederick, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 2/500 ;
U.S. Cl.
CPC ...
G01R 2/500 ;
Abstract

A phase measurement circuit includes first and second complementary clock strobe inputs, a local clock input and a sample clock output. A programmable delay line is coupled between the local clock input and the sample clock output and has a plurality of propagation delay settings. First and second toggle circuits are clocked by the first and second clock strobe inputs, respectively, and each has a toggle output that changes state when clocked by the respective first or second clock strobe input. A capture latch circuit has first and second data inputs coupled to the toggle outputs of the first and second toggle circuits, respectively, has first and second capture outputs, and is clocked by the sample clock output. A synchronizer circuit has first and second data inputs coupled to the first and second capture outputs, respectively, has first and second synchronized capture outputs, and is clocked by the local clock input.


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